MC8641DVU1500KE

Product Summary

The MC8641DVU1500KE is a Integrated Host Processor.

Parametrics

MC8641DVU1500KE absolute maximum ratings : (1)Cores supply voltages : -0.3 to 1.21 V; (2)Cores PLL supply : -0.3 to 1.21 V; (3)SerDes Transceiver Supply (Ports 1 and 2) : -0.3 to 1.21 V; (4)SerDes Serial I/O Supply Port 1 : -0.3 to 1.21V; (5)SerDes Serial I/O Supply Port 2 : -0.3 to 1.21 V; (6)SerDes DLL and PLL supply voltage for Port 1 and Port 2 : -0.3 to 1.21 V; (7)Platform Supply voltage : -0.3 to 1.21 V; (8)Local Bus and Platform PLL supply voltage : -0.3 to 1.21 V; (9)DDR and DDR2 SDRAM I/O supply voltages : -0.3 to 2.75 V 3; (10)eTSEC 1 and 2 I/O supply voltage : -0.3 to 3.63 V; (11)eTSEC 3 and 4 I/O supply voltage : -0.3 to 3.63 V; (12)Local Bus, DUART, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test, Power management, I2C, JTAG and Miscellaneous I/O voltage : -0.3 to 3.63 V.

Features

MC8641DVU1500KE features: (1)MPX coherency module (MCM) : Ten local address windows plus two default windows; (2)Optional low memory offset mode for core 1 to allow for address disambiguation; (3)Address translation and mapping units (ATMUs) : Eight local access windows define mapping within local 36-bit address space; (4)Inbound and outbound ATMUs map to larger external address spaces; (5)Three inbound windows plus a configuration window on PCI Express; (6)Four inbound windows plus a default window on serial RapidIO; (7)Four outbound windows plus default translation for PCI Express; (8)Eight outbound windows plus default translation for serial RapidIO with segmentation and sub-segmentation support; (9)DDR memory controllers : Dual 64-bit memory controllers (72-bit with ECC); (10)Support of up to a 300-MHz clock rate and a 600-MHz DDR2 SDRAM; (11)Support for DDR, DDR2 SDRAM; (12)Up to 16 Gbytes per memory controller; (13)Cache line and page interleaving between memory controllers; (14)Serial RapidIO interface unit : Supports RapidIO Interconnect Specification, Revision 1.2; (15)Both 1x and 4x LP-Serial link interfaces; (16)Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps) per lane; (17)RapidIO-compliant message unit; (18)RapidIO atomic transactions to the memory controller; (19)PCI Express interface : PCI Express 1.0a compatible; (20)Supports x1, x2, x4, and x8 link widths; (21)2.5 Gbaud, 2.0 Gbps lane; (22)Four enhanced three-speed Ethernet controllers (eTSECs) : Three-speed support (10/100/1000 Mbps); (23)Four IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers; (24)Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI; (25)Support a full-duplex FIFO mode for high-efficiency ASIC connectivity; (26)TCP/IP off-load; (27)Header parsing; (28)Quality of service support; (29)VLAN insertion and deletion; (30)MAC address recognition; (31)Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III programming models; (32)RMON statistics support; (33)MII management interface for control and status; (34)Programmable interrupt controller (PIC) : Programming model is compliant with the OpenPIC architecture; (35)Supports 16 programmable interrupt and processor task priority levels; (36)Supports 12 discrete external interrupts and 48 internal interrupts; (37)Eight global high resolution timers/counters that can generate interrupts; (38)Allows processors to interrupt each other with 32b messages.

Diagrams