EPM1270T144I5N

Product Summary

The EPM1270T144I5N is an instant-on, non-volatile CPLD. It is based on a 0.18μm, 6-layer-metal-flash process, with densities from 240 to 2,210 logic elements (LEs) (128 to 2,210 equivalent macrocells) and non-volatile storage of 8 Kbits. The EPM1270T144I5N offers high I/O counts, fast performance, and reliable fitting versus other CPLD architectures. Featuring MultiVolt core, a user flash memory (UFM) block, and enhanced in-system programmability(ISP), the EPM1270T144I5N is designed to reduce cost and power while providing programmable solutions for applications such as bus bridging, I/O expansion, power-on reset(POR) and sequencing control, and device configuration control.

Parametrics

EPM1270T144I5N absolute maximum ratings: (1)VCCINT, Internal Supply voltage With respect to ground: –0.5 to 4.6 V; (2)VCCIO, I/O Supply Voltage: –0.5 to 4.6 V; (3)VI, DC input voltage: –0.5 to 4.6 V; (4)IOUT, DC output current, per pin: –25 to 25 mA; (5)TSTG, Storage temperature No bias: –65 to 150℃; (6)TAMB, Ambient temperature Under bias: –65 to 135℃; (7)TJ, Junction temperature: 135℃.

Features

EPM1270T144I5N features: (1)Low-cost, low-power CPLD ; (2)Instant-on, non-volatile architecture; (3)Standby current as low as 2 mA ; (4)Provides fast propagation delay and clock-to-output times; (5)Provides four global clocks with two clocks available per logic array block (LAB); (6)UFM block up to 8 Kbits for non-volatile storage; (7)MultiVolt core enabling external supply voltages to the device of either 3.3 V/2.5 V or 1.8 V ; (8)MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, and 1.5-V logic levels; (9)Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors; (10)Schmitt triggers enabling noise tolerant inputs (programmable per pin); (11)Fully compliant with the Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 66 MHz ; (12)Supports hot-socketing; (13)Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (14)ISP circuitry compliant with IEEE Std. 1532.

Diagrams