TMS32C6414EGLZA5E0

fixed-point digital signal processor, BGA532, Highest-Performance, Twenty-Eight Operations/Cycle, 3.3V

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Price:: US $40.00~100.00 / piece [Get Latest Price]

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PartNumber:: TMS32C6414EGLZA5E0

Brand:: Texas Instruments - TI | Pack: BGA | D/C: 08+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-10-20

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Part Number:TMS32C6414EGLZA5E0
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Product Summary

The TMS32C6414EGLZA5E0 is a highest-performance fixed-point digital signal processor. The TMS32C6414EGLZA5E0 is based on the second-generation high-performance, advanced VelociTI very-long instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making the DSP an excellent choice for multichannel and multifunction applications. The TMS32C6414EGLZA5E0 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals.

Parametrics

TMS32C6414EGLZA5E0 absolute maximum ratings: (1)Supply voltage ranges: CVDD:- 0.3V to 1.8V, DVDD:-0.3V to 4V; (2)Input voltage ranges: (except PCI), VI:-0.3 V to 4 V; (3)Output voltage ranges: (except PCI), VO:-0.3 V to 4 V; (4)Operating case temperature ranges, TC:0℃ to 90℃; (5)Storage temperature range, Tstg:-65℃ to 150℃.

Features

TMS32C6414EGLZA5E0 features: (1)2-, 1.67-, 1.39-ns Instruction Cycle Time; (2)500-, 600-, 720-MHz Clock Rate; (3)Eight 32-Bit Instructions/Cycle; (4)Twenty-Eight Operations/Cycle; (5)4000, 4800, 5760 MIPS; (6)Fully Software-Compatible With C62x; (7)C6414/15/16 Devices Pin-Compatible; (8)Non-Aligned Load-Store Architecture; (9)64 32-Bit General-Purpose Registers; (10)Instruction Packing Reduces Code Size; (11)All Instructions Conditional; (12)Byte-Addressable (8-/16-/32-/64-Bit Data); (13)8-Bit Overflow Protection; (14)Bit-Field Extract, Set, Clear; (15)Normalization, Saturation, Bit-Counting; (16)VelociTI.2 Increased Orthogonality; (17)Supports up to 7 2-Mbps or 43 384-Kbps 3GPP (6 Iterations); (18)Programmable Turbo Code and Decoding Parameters; (19)Sixteen General-Purpose I/O (GPIO) Pins; (20)Flexible PLL Clock Generator; (21)IEEE-1149.1 (JTAG) Boundary-Scan-Compatible; (22)532-Pin Ball Grid Array (BGA) Package; (23)(GLZ and ZLZ Suffix), 0.8-mm Ball Pitch; (24)0.13-μm/6-Level Cu Metal Process (CMOS); (25)3.3-V I/Os, 1.2-V/1.25-V Internal (500 MHz) ; (26)3.3-V I/Os, 1.4-V Internal (600 and 720 MHz).