EPM7512AEQC208-10N

Product Summary

The EPM7512AEQC208-10N is a high-density, high-performance PLD. It is based on Altera’s second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7512AEQC208-10N provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz. The EPM7512AEQC208-10N has several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.

Parametrics

EPM7512AEQC208-10N absolute maximum ratings: (1)Supply voltage:–2.0V to 7.0V; (2)DC input voltage:–2.0V to 7.0V; (3)DC output current, per pin:–25mA to 25 mA; (4)Storage temperature:–65℃ to 150℃; (5)Ambient temperature:–65℃ to 135℃; (6)Junction temperature:Ceramic packages, under bias:150℃, PQFP and RQFP packages, under bias:135℃.

Features

EPM7512AEQC208-10N features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices:ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates; (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect); (7)PCI-compliant devices available; (8)Open-drain output option in MAX 7000S devices; (9)Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls; (10)Programmable power-saving mode for a reduction of over 50% in each macrocell; (11)Configurable expander product-term distribution, allowing up to 32 product terms per macrocell; (12)Six pin- or logic-driven output enable signals; (13)Two global clock signals with optional inversion; (14)Enhanced interconnect resources for improved routability; (15)Fast input setup times provided by a dedicated path from I/O ; (16)pin to macrocell registers; (17)Programmable output slew-rate control.

Diagrams