TMS320VC5509APGE

digital signal processor, QFP, -0.3 V to 4.0 V, High-Performance, Low-Power

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Price:: US $1.00~100.00 / piece [Get Latest Price]

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	US $1.00~100.00

PartNumber:: TMS320VC5509APGE

Brand:: Texas Instruments - TI | Pack: QFP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-10-21

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Part Number:TMS320VC5509APGE
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Product Summary

The TMS320VC5509APGE fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU of the TMS320VC5509APGE supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses of TMS320VC5509APGE provide the ability to perform up to three data reads and two data writes in a single cycle.

Parametrics

TMS320VC5509APGE absolute maximum ratings: (1)Supply voltage I/O range, DVDD: -0.3 V to 4.0 V; (2)Supply voltage core range, CVDD: -0.3 V to 2.0 V; (3)Input voltage range, VI: -0.3 V to 4.5 V; (4)Output voltage range, VO: -0.3 V to 4.5 V; (5)Operating case temperature range, TC: -40℃ to 85℃; (6)Storage temperature range, Tstg: -55℃ to 150℃.

Features

TMS320VC5509APGE features: (1)High-Performance, Low-Power, Fixed-Point TMS320C55x Digital Signal Processor: 9.26-, 6.95-, 5-ns Instruction Cycle Time, 108-, 144-, 200-MHz Clock Rate, One/Two Instruction(s) Executed per Cycle, Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)], Two Arithmetic/Logic Units (ALUs), Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses; (2)128K x 16-Bit On-Chip RAM, Composed of: 64K Bytes of Dual-Access RAM (DARAM) 8 Blocks of 4K × 16-Bit, 192K Bytes of Single-Access RAM (SARAM) 24 Blocks of 4K × 16-Bit; (3)64K Bytes of One-Wait-State On-Chip ROM (32K × 16-Bit); (4)8M × 16-Bit Maximum Addressable External Memory Space (Synchronous DRAM).